The present invention relates to a semiconductor device having a narrow contact formed in an interval between electrodes in a self-alignment manner, and also relates to a method of manufacturing the semiconductor device.
Recently, the integration level in LSI has been increased more and more. The increase in the integration level is particularly significant in DRAMs, SRAMs, Flush EEPROMs, and gate arrays.
As shown in FIG. 1, to compensate a positional deviation of a contact hole 32 from a metal wiring 31, an alignment clearance has been required. However, the improvement of the integration level is prevented by the presence of the alignment clearance d1. Then, a technology has been developed to form the contact without the alignment clearance d1, as shown in FIG. 1B.
FIG. 2A shows an alignment clearance d12 formed between a contact hole 33 for a diffusion layer and a gate electrode 34. Whereas, FIG. 2B shows a contact hole 33 formed by a self-alignment technique. From these, it is clear that when the contact hole is formed by the self-alignment technique, the interval between adjacent gate electrodes 34 can be minimized.
The self-alignment technique must involve an idea for keeping an insulation state between the gate electrode and the contact electrode even if the contact hole is overlapped with the gate electrode.
FIG. 3 shows the technical idea. To explain the idea more specifically, the gate electrode 34 is covered with silicon nitride films 36 and 37. An interlayer insulating film (oxide film) 36 is deposited on the silicon nitride films. The interlayer insulating film 35 is etched to form a contact hole. Since an etching selective ratio of the oxide film 35 to the silicon nitride films 36 and 37 is large, the silicon nitride films 36 and 37 covering the gate electrode 34 remain without being etched, even if the etching position on the interlayer insulating film 35 is slightly shifted toward the gate electrode 34. It is therefore possible to maintain the insulating state between the gate electrode 34 and the contact electrode of a diffusion layer 38. Note that the silicon nitride film 36 formed on side walls of the gate electrode 34 is referred to also as "spacer layer", and the silicon nitride film 37 formed over the gate electrode 34 is referred to also as "cap layer". Such silicon nitride films may be one of the most important factors to form the contact hole 33 in a self alignment manner.
On the other hand, to accelerate an operation speed of LSI, it has been required to reduce the sheet resistance of the gate electrode and source/drain regions. This requirement can be satisfied by the newly developed technique called salicide technique. As known well, "salicide" is an abbreviation of "Self-Aligned Silicide". The "silicide" used herein is a compound of a semiconductor and a metal.
As shown in FIG. 4, a silicide layer 39 is formed on the surface portions of the gate electrode 34 and the source/drain region 38. The silicide layer 39 is formed by depositing a metal with a high melting point on the gate electrode 34 (polysilicon) and the source/drain region 38 (silicon), followed by heating.
It has been desired to employ the salicide technique together with the self-alignment technique for the contact hole, since the combination of the techniques will overcome two big problems associated with LSI, namely, "high-speed operation" and "integration", simultaneously. However, this idea has not yet been realized. This is because the gate electrode 34 is patterned after the silicon nitride film is deposited on the surface of a polysilicon wafer. To be more specific, since the surface of the gate electrode 34 patterned is covered with a silicon nitride film (cap layer) 37, the metal having a high melting point cannot be deposited on the surface of the polysilicon gate electrode 34.
If the gate electrode is patterned after the silicide layer is formed on the surface layer portion of the polysilicon wafer and the silicon nitride film is formed on the silicide layer, the aforementioned two techniques may be used together. However, to realize it, a cost increase is inevitable and a masking step must be added.